1. Field of the Invention
Embodiments of the invention relate generally to the field of memory devices and more particularly, to a system and method for biasing lines in semiconductor memories.
2. Description of the Related Art
Flash memory is a non-volatile memory that can be electrically erased and reprogrammed. It is primarily used in memory cards, USB flash drives, and the like, for storage of data in computer systems. Generally, flash memory stores information in an array of floating gate transistors, called “cells”, each of which traditionally stores one bit of information that is represented as a “0” or a “1”. The memory device often includes a grid-like arrangement of the cells and associated transistors. Each of the cells in the grid consumes a given amount of area and is spaced from one another by a generally uniform distance (e.g., pitch). Accordingly, the size and the pitch of the cells directly contribute to the overall size of the memory device. This becomes more evident as the number of cells and associated storage capacity of memory devices increase.
As technology continues to advance, it is desirable that memory devices decreases in size. Smaller memory devices can be employed in smaller spaces and/or can increase storage capacity in a limited area or volume. One technique for reducing the memory device size typically includes reducing the size (e.g., scaling) of the memory cell and associated transistors. Unfortunately, as the cells and associated transistors are scaled, physical limitations may undesirably reduce the performance of the memory device. For example, the memory cells and associated transistors are scaled, the tunnel oxide thickness in a high-voltage (HV) transistor may become so thin that it cannot reliably hold electrons on the floating gate of the cell. As a result, the cell may not reliably store data over an extended period of time. For example, it will be appreciated that the tunnel oxide thickness of flash memory cells is based on the data retention characteristics and in typically within about 7-10 nm (nano meters). This thickness may be critical, as the cells may have to retain the charges for an extended period (e.g., 10 years). Because programming voltage on word-lines results in such a high voltage (e.g., 15-25V), the gate oxide thickness in the decoding or access transistors may be about 30-40 nm which can limit the decoding or accessing transistor channel length to about 2-3 micro meters (um). Unfortunately, this may limit the reduction of cell and transistor size and, thus, limit scaling of the entire memory device.
Embodiments of the present invention may be directed to one or more of the problems set forth above.